DC-DC converters are used to convert an input DC voltage to an output DC voltage. In one class of DC-DC converters, known as switching mode converters, the output voltage is determined by the duty cycle of a switch to which the input voltage is applied.
An example of a switching mode DC-DC converter is the complementary synchronous buck converter 10 shown in FIG. 1. A complementary pair of MOSFETs M1 and M2 are connected in series between the input voltage V.sub.in and ground, P-channel MOSFET M1 serving as a series switch and N-channel MOSFET M2 serving as a shunt switch. The common node between MOSFETs M1 and M2 is connected through a low-pass filter including an inductor L1 and a capacitor C1 which deliver the output voltage V.sub.out to the load. V.sub.out is fed back to a pulse width modulation (PWM) control 12, which supplies a PWM signal to the gates of MOSFETs M1 and M2. V.sub.out is determined by the duty cycle of the PWM signal, i.e., in this case the percentage of the time during each cycle that the PWM signal is low, thereby turning P-channel MOSFET M1 on. PWM control 12 is controlled by the feedback path to maintain V.sub.out at a desired level.
DC-DC converters are available in a wide variety of topologies. FIG. 2 shows a totem pole N-channel synchronous buck converter 20, in which V.sub.out is determined by the duty cycle of high segment of the PWM signal applied to the gate of N-channel MOSFET M3. PWM control 22 supplies time delayed signals to the respective gates of MOSFETs M3 and M4 so as to prevent current "shoot through" from V.sub.in to ground. FIG. 3 shows a boost converter 30 which includes an N-channel MOSFET M5 and a Schottky diode 32.
A common feature of the converters shown in FIGS. 1-3, as well as numerous other converter topologies, is that one or more power MOSFET switches are used to control the transfer of energy from an energy source, here represented by V.sub.in, into at least two reactive energy storage elements, namely an inductor and a capacitor. These energy storage elements then retransfer the stored energy, when required, into the load. By monitoring V.sub.out and by either controlling the pulse width of the signal which controls the MOSFET switches (assuming that the converter is operating at a fixed frequency), or adjusting the switching frequency (while holding the on-time of the switches constant), a constant V.sub.out can be maintained, despite changes in V.sub.in or the current demands of the load.
Of the various switching mode converter topologies and control schemes, fixed frequency converters provide a predictable noise spectrum. A predictable noise spectrum is particularly advantageous in communication products, such as cellular phones, since shifting noise spectra can interfere with information transfer in the broadcast band. With a fixed clock period, the energy transfer is a function of the switch on-time (or pulse width), which is modulated to compensate for an energy drain or a voltage build-up at the output of the converter.
Most converters, in their essential configuration, include a PWM control circuit, an inductor, a capacitor, and two MOSFET switches (or one MOSFET switch and a Schottky diode). Ideally, every element transfers power without loss. In reality, of course, some power is lost in every element. The IC control circuit, for example, draws power to operate internal amplifier, voltage reference, comparator, and clock circuits. The inductor loses power to the resistance of its coil and to the material used as its magnetic core. Even the capacitor has a series resistance component which absorbs energy.
In practice, however, most of the power in a converter is lost in the power MOSFET that is used as the series switch and in the power MOSFET or Schottky diode that is used as the shunt switch or rectifier. These losses can be divided into four categories:
1. Conduction losses which arise from the MOSFETs' internal resistance, represented as I.sup.2 R.multidot.D, where I is the current through the switch, R is the on-resistance of the switch, and D is the percentage of the time that the switch is on.
2. Gate drive losses, or the power lost charging and discharging the MOSFETs' gate capacitance, represented as Q.sub.g .multidot.V.sub.gs .multidot.f, where Q.sub.g is the charge which accumulates on the gate, V.sub.gs is the gate-to-source voltage, and f is the frequency at which the switch is opened and closed.
3. Output capacitive losses, or the power lost charging and discharging the drain capacitance of the MOSFET switch, represented as C.sub.o .multidot.V.sub.ds.sup.2 .multidot.f.
4. Crossover losses, or losses which occur during the switching transitions of the MOSFETs, as a result of the simultaneous presence of a current through and a voltage across a MOSFET, represented as I.sub.on .multidot.V.sub.ds .multidot..delta.t, where I.sub.on is the current through the MOSFET during the switching transition and .delta.t is the duration of the switching transition.
The conduction losses are strongly dependent on the current and on-resistance while the gate drive and output capacitive losses are strongly dependent on the switching frequency. At low frequencies, particularly below 100 kHz, only the conduction losses need to be considered when calculating the efficiency of the converter. At higher frequencies, particularly frequencies approaching 1 MHz, the capacitive losses become significant. V.sub.in and V.sub.out affect all of the energy loss terms. In high voltage converters the output capacitance term can be dominant. In low voltage applications such as computers and battery powered circuits, however, particularly those in which V.sub.in is less than 8 volts, the output capacitance term is negligible. The two dominant terms are then the gate drive and conduction losses, and the power loss can be approximated by the following equation. EQU P.sub.loss =Q.sub.g (V.sub.gs).multidot.V.sub.gs .multidot.f+I.sup.2 .multidot.R.sub.ds (V.sub.gs).multidot.(t.sub.on (V.sub.in)/T)
An increase in the gate drive V.sub.gs reduces R.sub.ds and conduction losses but increases gate drive capacitance losses. The frequency f and the load current I are weighting factors which determine which term is dominant. At higher frequencies, the gate drive capacitance loss becomes significant for all light load conditions.
FIGS. 4A-4J are graphs which illustrate how the efficiency and other parameters of a P-channel DMOS switch used in a synchronous buck converter (corresponding to P-channel MOSFET M1 in FIG. 1) vary as a function of the channel size or resistance of the P-channel DMOS switch.
Referring to FIG. 4A, the x-axis represents the die size of the P-channel buck switch normalized such that unity equals the size of a standard S0-8 package (approximately 90 mils.times.190 mils). Curve P1 shows the percentage of the total losses due to the gate capacitance C.sub.g, curve P2 shows the percentage of the losses due to the switching of the MOSFET, and curve P3 shows the percentage of losses due to the on-resistance of the P-channel (R.sub.ds (on)). Curve P4 shows the efficiency of the P-channel switch. The input (battery) voltage V.sub.b was 3.5 V, the output voltage V.sub.o was 2.7 V. the load current I was 0.3 A, and the buck converter was operated at a frequency f of 1 MHz. As is apparent, at low die sizes, the resistance losses (curve P3) dominate, while at large die sizes the capacitance losses (curve P1) dominate. The efficiency of the buck converter (curve P4) reaches a maximum at a normalized die size of about 0.2, which is the optimum die size for this set of parameters.
FIG. 4B shows the same data as a function of the channel resistance of the of the P-channel switch (in .OMEGA.). Curve P5 represents the percentage of losses due to C.sub.g, curve P6 represents the percentage of losses due to switching losses, curve P7 represents the percentage of losses due to R.sub.ds (on), and curve P8 represents the efficiency of the P-channel switch.
FIGS. 4A and 4B indicate that the efficiency of the switch reaches a maximum. If the die size is either too large or too small the efficiency will suffer. Another factor which affects efficiency is the input voltage V.sub.b.
FIG. 4C shows the efficiency as a function of die size (normalized as in FIG. 4A) at three levels of V.sub.b. Curve P9 represents V.sub.b =3.0 V, curve P10 represents V.sub.b =3.5 V, and curve P11 represents V.sub.b =4.2 V. FIG. 4D shows the same data as a function of channel resistance. V.sub.o, I and f are at the same levels as in FIGS. 4A and 4B. FIGS. 4C and 4D indicate that different die sizes and channel resistances are optimal depending on the level of the battery voltage that is being fed into the converter. The range of V.sub.b shown in FIGS. 4C and 4D corresponds roughly to the variation that occurs normally in a lithium ion battery as it fluctuates between a charged and discharged condition. When the battery is discharged (low V.sub.b), the buck switch must be turned on a larger percentage of the time in order to keep the output voltage; thus, because R.sub.ds (on) is more important in determining efficiency, it is preferable to have a larger die. Conversely, when the battery is fully charged (high V.sub.b), the gate capacitance C.sub.g becomes more significant, and it is therefore preferable to have a smaller die.
While the actual maximum efficiency also varies with the battery voltage as shown in FIG. 4C, this is not the major problem. The main problem is that optimal size of the die for the buck switch varies from about 0.18 for a fully charged battery to about 0.25 for a medium battery to about 0.32 for a discharged battery.
Another factor which affects the efficiency of the PMOS switch is the load current I. FIG. 4E shows efficiency as a function of normalized die size for load currents of 0.9 A (curve P15), 0.3 A (curve P16) and 0.1 A (curve P17). The range from 0.9 A to 0.1 A corresponds, for example, to the load current used in a cellular phone as it goes from the transmit mode to the receive mode. Again, the efficiency of the switch varies greatly, as would be expected from the I.sup.2 .multidot.R.sub.ds term in the above equation for P.sub.loss. As I.sup.2 becomes greater, the value of R.sub.ds becomes more significant as a weighting factor, and a larger die becomes advantageous. To appreciate the importance of the load current, note that at I=0.9 A the peak efficiency occurs at die size of about 0.5, while at I=0.1 A the peak efficiency occurs at a die size of about 0.1. In other words, the size of the die would have to vary by a factor of about five in order to obtain maximum efficiency at both high and low load currents. Looking at the matter another way, if a die size of 0.25 were selected to maximize the efficiency (95%) at I=0.3 A, the efficiency of the switch would fall to about 92% in the high current condition and to about 90% in the low current condition. This in itself might be acceptable, but recall that the efficiency of the switch also varies with the battery voltage. The two effects are additive. The combined effects could create unacceptably low levels of efficiency.
FIG. 4F shows the same data as FIG. 4E as a function of channel resistance.
FIGS. 4G and 4H show the same data as FIGS. 4E and 4F, respectively, except that the low current has been reduced from 0.1 A to 0.05 A and, in FIG. 4G, the horizontal axis has been limited to a normalized die size ranging from 0.05 to 0.4, which is the interval of interest. The peak efficiency at the low current occurs at a die size that is well under 0.1. At that die size, if the current suddenly went to 0.9 A the efficiency would drop all the way down to around 77%. Clearly, a die size of less than 0.1 is completely incompatible with the high current condition.
FIGS. 4I and 4J show the same data as FIGS. 4G and 4H, respectively, plotted on semilog paper.
The main point is that all of these figures show significant variations in the optimum die size for different levels of current. At light current conditions, one way to improve efficiency is to reduce the gate drive losses (the Q.sub.g V.sub.gs f term in the above equation). Once V.sub.gs (which is the same as the battery voltage V.sub.b) has been set, the amount of charge Q.sub.g is determined by the die size. That leaves the frequency f is the only remaining variable, and in fact one way to solve the problem is to switch to a lower frequency at light load conditions. For example, if the converter is normally operating at 1 Mhz, the frequency could be reduced by an order of magnitude to 100 kHz, or even two orders of magnitude to 10 kHz. As a result the Q.sub.g V.sub.gs f term becomes insignificant and only conduction losses are present at light load conditions. The problem with this solution is that switching the frequency takes a finite amount of time. For example, if the current suddenly increases and the efficiency falls to 65% or 70%, it takes some time to increase the frequency back up to the normal level. During the time interval while the converter is trying to speed up to the high frequency, the output voltage sags. Conversely, when the converter attempts to reduce the frequency, the output voltage may overshoot. In either case, voltage regulation is momentarily lost. Moreover, frequency shifting produces a range of harmonics which cannot readily be filtered out. This can present serious problems, particularly for converters that are used in communications equipment.
There is therefore a need for a MOSFET and a DC-DC converter design which provide low gate capacitive losses during light load conditions while providing low conduction losses during normal load conditions, without relying on frequency shifting or burst mode techniques.